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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:47:15 12/15/2016 
-- Design Name: 
-- Module Name:    makecode_to_ascii - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity makecode_to_ascii is
    Port ( make_in : in  STD_LOGIC_VECTOR (7 downto 0);
           ascii_out : out  STD_LOGIC_VECTOR (7 downto 0));
end makecode_to_ascii;

architecture Behavioral of makecode_to_ascii is

begin
	with make_in select
		ascii_out <= x"41" when x"1C", --A
						 x"42" when x"32", --B
						 x"43" when x"21", --C
						 x"44" when x"23", --D
						 x"45" when x"24", --E
						 x"46" when x"2B", --F
						 x"47" when x"34", --G
						 x"48" when x"33", --H
						 x"49" when x"43", --I
						 x"4A" when x"3B", --J
						 x"4B" when x"42", --K
						 x"4C" when x"4B", --L
						 x"4D" when x"3A", --M
						 x"4E" when x"31", --N
						 x"4F" when x"44", --O
						 x"50" when x"4D", --P
						 x"51" when x"15", --Q
						 x"52" when x"2D", --R
						 x"53" when x"1B", --S
						 x"54" when x"2C", --T
						 x"55" when x"3C", --U
						 x"56" when x"2A", --V
						 x"57" when x"1D", --W
						 x"58" when x"22", --X
						 x"59" when x"35", --Y
						 x"5A" when x"1A", --Z
						 x"30" when x"45", --0
						 x"31" when x"16", --1
						 x"32" when x"1E", --2
						 x"33" when x"26", --3
						 x"34" when x"25", --4
						 x"35" when x"2E", --5
						 x"36" when x"36", --6
						 x"37" when x"3D", --7
						 x"38" when x"3E", --8
						 x"39" when x"46", --9
						 x"20" when x"29", --Space
	                x"20" when others;

end Behavioral;